1. Field of the Invention
The present invention relates to a test device and method for measuring the true effects of negative bias temperature instability (NBTI) of PFETs (p-channel field effect transistors).
2. Description of the Related Art
High performance PFETs (p-channel field effect transistors) with p+ polysilicon doped gates have been found to exhibit an instability after voltage/temperature aging. This phenomenon is known as xe2x80x9cnegative bias temperature instabilityxe2x80x9d (NBTI). The instability occurs under negative gate voltage and is measured as an increase in the magnitude of threshold voltage of the device. Higher stress temperatures produce more degradation. The mechanism is known to cause reliability performance degradation for the PFET because of this change in threshold voltage.
Several physical models have been proposed in the literature. Basically, an electro-chemical reaction presumably occurs in the gate oxide, due to sensitivity of p+ gates to moisture trapping. The result is a net positive charge in the gate oxide, causing a bias effect that affects threshold voltage.
The degradation caused is exponential with oxide electric field. This problem is getting much worse with each generation of CMOS scaling in which oxide thickness is aggressively scaled down but voltage scaling does not keep pace with the oxide thickness scaling. The mechanism, therefore, becomes a major technology reliability scaling problem.
A relaxation of the degradation has been observed when the DC stress is turned xe2x80x9cOFFxe2x80x9d following an xe2x80x9cONxe2x80x9d stress. Relaxation is a phenomenon known to occur in charge trapping mechanisms.
A stress bias configuration of the PFET 10 is shown in FIG. 1, where a positive voltage 16 is applied to the diffusions 13,14 and the N-well 12 while the gate 15 of the PFET is at ground potential. This stress bias configuration can alternatively be replaced by the configuration shown in FIG. 2 where a negative voltage 21 is applied to the gate while all other terminals of the FET are at ground.
FIG. 3 shows the effect of stress on the drain-to-source current versus gate voltage characteristic 30 of the FET 10. The bias temperature aging under the configuration of FIG. 1 produces an increase 31 in the absolute value of the threshold voltage (Îxe2x80x3Vth), which in turn causes a decrease in the drain-to-source current (Id) for a given gate-to-source voltage (Vg). Again, this PFET device instability is usually referred to as a negative bias temperature instability (NBTI) since it requires the applications of a negative gate voltage for the mechanism to be active. The change in threshold voltage and the corresponding decrease in device current could cause signal delay or performance degradation in operating circuits utilizing such devices.
There are numerous publications dealing with the characteristics, behavior and physics of the NBTI mechanism. From this literature, it is found that the magnitude of change in threshold voltage after stress for a time duration t under gate voltage of V and temperature T is given by:
xe2x80x83|xcex94Vth|=A e(xe2x88x92xcex94H/KT)e(xe2x88x92xcex3Tox/V)tnxe2x80x83xe2x80x83(Equation 1),
where |Îxe2x80x3Vth| is the magnitude of final threshold voltage value after stress minus its initial value before stress; A, Î3, and n are constants (positive values) that are dependent upon the particular technology in question; Îxe2x80x3H is referred to as the activation energy; Tox is the oxide thickness, and K is Boltzmann""s constant.
FIG. 4 shows a typical behavior of |Îxe2x80x3Vth| with a straight line relationship (slope=n) versus time on a logxe2x80x94log scale, as predicted by equation (1). The behavior of the NBTI mechanism described in the literature is the DC stress mode where the stress conditions of FIG. 1 are applied. This DC stress mode of FIG. 1 will be referred to as the xe2x80x9cONxe2x80x9d stress condition, and the behavior of |Îxe2x80x3Vth| in this case is given by equation (1).
The increase in the absolute value of the threshold voltage due to the NBTI mechanism is a serious technology reliability problem because it leads to performance degradation and subsequent failure of semiconductor integrated chips. Because this mechanism depends on oxide thickness, as shown in the above equation 1, the degradation caused by the NBTI becomes worse as the oxide thickness is reduced (i.e., as CMOS technology scaling continues and as the drive for better performance intensifies). An important aspect of dealing with this problem is the ability to determine the actual impact of this mechanism on the reliable performance of integrated chips where devices are mostly subjected to pulsed voltage conditions rather than DC conditions.
This is illustrated in FIG. 5, which shows a simple CMOS inverter 50 where the input voltage changes from ground potential to a value of V with a period of Ïxe2x80x3, and the output voltage is the complement of the input. Excluding transient conditions, the PFET of this CMOS inverter is subjected to two stress configurations. The first configuration is when the output voltage is equal to V, i.e., the gate of the PFET is at ground, and this condition is what has been referred to as the xe2x80x9cONxe2x80x9d stress condition.
The second configuration, as shown in FIG. 6, is referred to as the xe2x80x9cOFFxe2x80x9d stress condition, i.e., when the gate 15 of the PFET 10 is at voltage V, one diffusion is also at voltage V while the other diffusion is at ground. But, as mentioned above, the behavior of the NBTI mechanism is represented by equation (1) as a DC xe2x80x9cONxe2x80x9d stress.
More realistic to the actual operation of the CMOS inverter, the more realistic question is that of asking what happens to the device under conditions of an xe2x80x9cONxe2x80x9d stress, followed by an xe2x80x9cOFFxe2x80x9d stress. FIG. 7A (Case 1) shows the behavior of |Îxe2x80x3Vth| versus time when the PFET is subjected to an xe2x80x9cONxe2x80x9d stress (A) for a duration of 20 seconds, followed by an xe2x80x9cOFFxe2x80x9d stress (B) for a duration of 1200 seconds with measurements of |Îxe2x80x3Vth| (readouts) at 10 sec, 20 sec, 60 sec., 180 sec., and 1200 sec. (all measured from the start of the xe2x80x9cOFFxe2x80x9d stress), and then followed by another xe2x80x9cONxe2x80x9d stress (Axe2x80x2) for a duration of 20 seconds. The magnitude of the stress voltage was 4.2 V, and the stress temperature was 140Âxc2x0 C.
Even though the magnitude of the threshold voltage shift (C) was small under these conditions, it is noticeable that the xe2x80x9cOFFxe2x80x9d stress following the xe2x80x9cONxe2x80x9d stress caused |Îxe2x80x3Vth| to decrease measurably. Thus, there is some relaxation effect due to the xe2x80x9cOFFxe2x80x9d stress following the xe2x80x9cONxe2x80x9d stress.
In FIG. 7B, the behavior of Case 1 shown in FIG. 7A was replotted. This time the effective time (A, Axe2x80x2) under xe2x80x9cONxe2x80x9d stress condition is indicated on the X-axis of the plot (meaning that all time intervals for xe2x80x9cOFFxe2x80x9d stress were not included on the X-axis). The Y-axis for |Îxe2x80x3Vth| of FIG. 7B includes the relaxation effect of the xe2x80x9cOFFxe2x80x9d stress. It is clear that the behavior of the PFET under pulsed voltage conditions, i.e., repeated combinations of xe2x80x9cOFFxe2x80x9d and xe2x80x9cONxe2x80x9d stressing, would be more complicated than the DC model under xe2x80x9cONxe2x80x9d stress, and thus it would be extremely difficult to theoretically predict the actual effect of the NBTI mechanism on the performance of CMOS integrated circuits, and to determine the effect of technology scaling and the effect of different processing conditions.
Thus, a system needs to be developed to determine the impact of the NBTI reliability mechanism on the performance of CMOS integrated circuits, under any conditions of cycle time (Ïxe2x80x3), which is the sum of the intervals for the xe2x80x9cONxe2x80x9d plus xe2x80x9cOFFxe2x80x9d stresses (Ïxe2x80x3=1/f, where f is the frequency or performance), duty factor (DF), which is xe2x80x9cONxe2x80x9d time relative to cycle time, and technology processing. Prior to the present invention, no such system has been known.
FIG. 8 illustrates the use of appliquxc3xa9s to realize a flow disturbance structure
The present invention solves the above stated problem by introducing a test circuit and method which can be used to measure the impact of NBTI reliability failure mechanism on the performance of CMOS products. As will be explained in more detail below, the present inventors have found that under a series of xe2x80x9cONxe2x80x9d and xe2x80x9cOFFxe2x80x9d stresses, the degradation behavior for the mechanism deviates from that predicted by the DC model. From both the underlying physics and actual bench stressing testing, it has been found by applying an AC-like stressing that a deviation occurs from the DC results. The deviation depends on frequency and duty factor of the AC stress test.
This invention provides a technology for determining the true and realistic effects of the NBTI mechanism. It is also vital to provide a technology to determine the actual effect and extent of degradation on functional circuits. The test system disclosed as part of this invention also accomplishes this second result. It is, therefore, an object of the present invention to provide a structure and method for accurately measuring the effects of the NBTI mechanism on CMOS.
It is another object of the present invention to teach a method of investigating the true effects of the NBTI mechanism using DC stress and AC stress testing techniques, either alone or in combination.
It is another object of the present invention to teach a test circuit and method of investigating the NBTI mechanism by providing the capability to systematically investigate a change in test parameters, including among others, cycle time, duty factor, voltage, temperature, and stress time.
It is another object of the present invention to teach a method of determining circuit reliability by including measurement of NBTI effects.
It is another object of the present invention to teach a method of in-line reliability testing of manufactured hardware in which disposition criteria are set up to include NBTI measurements.
The back side 26 further comprises a flow disturbance structure 34 that imparts a rippling effect to water that flows over the back side 26. The flow disturbance structure 34 is a series of substantially parallel grooves 36 of rectangular cross-section that are separated by a series of substantially parallel lands 38. The flow disturbance structure 34 is created by removing material from whatever material is used for the substrate 12 to create the grooves 36 and thereby create the lands 38. If a different rippling effect is desired, grooves with a different spacing, depth and/or profile (e.g., saw tooth) than the grooves 36 can be created. Further, grooves that are not parallel to one another can also be used to create a different rippling effect. It should also be appreciated that flow disturbance structures other than the flow disturbance structure 34 are possible. For instance, a flow disturbance structure of hemispherical blisters, pyramids, xe2x80x9cmoonsxe2x80x9d etc. or combinations there are possible. Further, it should also be appreciated that comparable flow disturbance structures can be realized by applying material to whatever material is used to create the substrate. For example, FIG. 8 illustrates the same flow disturbance structure 34 as shown in FIG. 4 but with the grooves 36 and lands 38 realized by the adherence of appliquxc3xa9s 92 to the substrate 12.
It is another object of the present invention to teach a method of measuring NBTI effects by correlation of a ring oscillator frequency with a shift in threshold voltage of a PFET.
It is another object of the present invention to teach a ring oscillator having an odd number of circuit elements, each having a programmable delay.
It is another object of the present invention to teach a ring oscillator having a variable duty cycle.
It is another object of the present invention to teach a ring oscillator having an odd number of circuit elements, each element being a non-inverting buffer stage.
It is another object of the present invention to teach a ring oscillator having a feature that oscillation can be started using an input control signal.
It is another object of the present invention to teach a ring oscillator with elements having a programmable delay and the programmable delay controlled by a binary word input.
It is another object of the present invention to teach an NBTI test method in which a single PFET is targeted by having a single one of the targeted PFETs incorporated in each stage of a ring oscillator.
It is another object of the present invention to teach a method of determining the magnitude and behavior of the degradation due to the NBTI mechanism under any desired AC conditions of voltage, duty factor, and frequency of any intended circuit applications.
It is another object of the present invention to teach a method that permits a determination of the difference between the degradation due to the NBTI mechanism under DC and AC conditions.
It is another object of the present invention to teach a method to determine the effect of the degradation due to the NBTI mechanism on technology scaling under actual AC operating conditions and from which an optimum and realistic path for technology scaling could be arrived at.
It is another object of the present invention to teach a procedure and methodology according to which a reliability in-line manufacturing control system is achieved to protect manufactured goods from any undesired degradation due to the NBTI mechanism.
To achieve the above goals and objectives, as a first aspect of the present invention, described herein is a ring oscillator including an odd number of elements interconnected in a serially-connected infinite loop, each element having an associated programmable delay feature.
As a second aspect of the present invention, described herein is a test circuit to measure a Negative Bias Temperature Instability (NBTI) effect for PFETs (p-channel MOSFET) by stressing a target PFET component with at least one stress condition, the target PFET component being integrated as a component into the test circuit, the target PFET component having a source, a drain, and a gate, the test circuit including a ring oscillator having an odd number of oscillator elements interconnected serially in an infinite loop, wherein at least one the target PFET component is integrated into the ring oscillator and a test output providing a point to measure at least one parameter of the ring oscillator.
As a third aspect of the present invention, described herein is a method of testing a PFET (p-channel field effect transistor) by incorporating a target PFET into a ring oscillator having an odd number of elements, performing at least one stress test on the PFET, and measuring at least one characteristic of at least one of the PFET and the ring oscillator.